Optimum Position of Digital DAC Error Correction relative to the Decimation Filter in ΔΣ ADCs
Author:
Affiliation:
1. University of Ulm Albert-Einstein-Allee 43,Institute of Microelectronics,Ulm,Germany
Funder
Ministry of Education
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10382705/10382711/10382885.pdf?arnumber=10382885
Reference8 articles.
1. Implementation of a low power decimation filter in a 180 nm hv-cmos technology for a neural recording front-end;Sporer
2. Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback
3. Continuous-Time $\Delta \Sigma $ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC
4. Hardware complexity of a correlation based background DAC error estimation technique for sigma-delta ADCs
5. A digital compensation method canceling static and non-linear time-variant feedback DAC errors in ΣΔ analog-to-digital converters
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