Below 45nm low-k layer stress minimization guide for high-performance flip-chip packages with copper pillar bumping
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5482824/5490635/05490766.pdf?arnumber=5490766
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Chip-Package interaction stress analysis and optimization for a 14nm extreme low-k chip of FCCSP package;2022 23rd International Conference on Electronic Packaging Technology (ICEPT);2022-08-10
2. The Optimal Solution of Fan-Out Embedded Bridge (FO-EB) Package Evaluation during the Process and Reliability Test;2022 IEEE 72nd Electronic Components and Technology Conference (ECTC);2022-05
3. Mechanical BEoL Stability Investigation at Cu-Pillars under Cyclic Load;2021 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA);2021-09-15
4. Fabrication and Reliability Assessment of Cu Pillar Microbumps With Printed Polymer Cores;Journal of Electronic Packaging;2021-01-19
5. Advanced Preclean Chamber for Ubm/Rdl Contact Resistance Improvement in Advanced Node Packaging Application;2020 International Wafer Level Packaging Conference (IWLPC);2020-10-13
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