Trap Identification in Gate-All-Around Vertically Stacked Si n-channel Nanosheet FETs
Author:
Affiliation:
1. Normandie University,ENSICAEN, CNRS, GREYC,Caen,France,14000
2. Imec,Leuven,Belgium,B-3001
3. Ghent University,Solid-State Sciences Department,Gent,Belgium,9000
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10472738/10472739/10472772.pdf?arnumber=10472772
Reference12 articles.
1. Low frequency noise versus temperature spectroscopy of recently designed Ge JFETs
2. Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration
3. Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization
4. Low frequency noise assessment in n- and p-channel sub-10nm triple-gate FinFETs: Part I: Theory and methodology
5. Low frequency noise analysis on Si/SiGe superlattice I/O n-channel FinFETs
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