An 8-Core 64-Thread 64b Power-Efficient SPARC SoC-Reference-Cited by-同舟云学术

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An 8-Core 64-Thread 64b Power-Efficient SPARC SoC

Published:2007-02 Issue: Volume: Page:
ISSN:0193-6530
Container-title:2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
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Author:

Nawathe Umesh Gajanan,Hassan Mahmudul,Warriner Lynn,Yen King,Upputuri Bharat,Greenhill David,Kumar Ashok,Park Heechoul

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4242240/4242241/04242288.pdf?arnumber=4242288

Cited by 22 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%–99.99% Error Coverage in Intel 4 CMOS;IEEE Journal of Solid-State Circuits;2024-01

2. A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS;IEEE Journal of Solid-State Circuits;2023-04

3. A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS;IEEE Journal of Solid-State Circuits;2021-04

4. A 4900-$\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition;IEEE Journal of Solid-State Circuits;2020-04

5. Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-07

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