A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery-Reference-Cited by-同舟云学术

A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

Published:2007-02 Issue: Volume: Page:
ISSN:
Container-title:2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
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Author:

Harwood Mike,Warke Nirmal,Simpson Richard,Leslie Tom,Amerasekera Ajith,Batty Sean,Colman Derek,Carr Eugenia,Gopinathan Venu,Hubbins Steve,Hunt Peter,Joy Andy,Khandelwal Pulkit,Killips Bob,Krause Thomas,Lytollis Shaun,Pickering Andy,Saxton Mark,Sebastio David,Swanson Graeme,Szczepanek Andre,Ward Terry,Williams Jeff,Williams Richard,Willwerth Tom

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4242240/4242241/04242452.pdf?arnumber=4242452

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