A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS-Reference-Cited by-同舟云学术

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A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS

Published:2011-02 Issue: Volume: Page:
ISSN:
Container-title:2011 IEEE International Solid-State Circuits Conference
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Author:

Abiri Behrooz,Shivnaraine Ravi,Sheikholeslami Ali,Tamura Hirotaka,Kibune Masaya

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5740653/5746170/05746261.pdf?arnumber=5746261

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of Digital Phase Interpolator for 6.25Gbps CDR Circuit;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

2. A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation;International Journal of Circuit Theory and Applications;2023-01-04

3. 4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop;IEICE Transactions on Electronics;2022-10-01

4. A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-01

5. A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation;IEEE Transactions on Circuits and Systems II: Express Briefs;2020-10

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