A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration-Reference-Cited by-同舟云学术

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A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration

Published:2010-02 Issue: Volume: Page:
ISSN:
Container-title:2010 IEEE International Solid-State Circuits Conference - (ISSCC)
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Author:

Ali Ahmed M.A.,Morgan Andy,Dillon Chris,Patterson Greg,Puckett Scott,Hensley Mike,Stop Russell,Bhoraskar Paritosh,Bardsley Scott,Lattimore David,Bray Jeff,Speir Carroll,Sneed Robert

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5428240/5433812/05433923.pdf?arnumber=5433923

Cited by 23 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An IF-Sampling CMOS S/H Calibration Technique With Analog HPF Slope Estimation;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-12

2. A Mismatch Error Calibration Method for 14-bit 500MS/s Time-interleaved Charge-Domain ADC;2022 7th International Conference on Integrated Circuits and Microsystems (ICICM);2022-10-28

3. A Compact Calibration Model for Linearizing CMOS Sample-and-Hold Circuits;IEEE Transactions on Circuits and Systems II: Express Briefs;2020-11

4. A 14-bit 250-MS/s charge-domain pipelined ADC with mix-signal foreground calibration;Analog Integrated Circuits and Signal Processing;2019-09-11

5. High Precision Mix‐Signal Capacitor Mismatch Error Calibration Method for Charge‐Domain Pipelined ADC;Chinese Journal of Electronics;2019-03

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