29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/7866667/7870233/07870476.pdf?arnumber=7870476
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Phase Noise Analysis for Stochastically Injected Oscillators;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-08
2. Optimal Distribution of High-Speed Clocks on Transceiver Chips;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
3. An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-02
4. 3.125-to-28.125 Gb/s 4.72 mW/Gb/s Multi- Standard Parallel Transceiver Supporting Channel-Independent Operation in 40-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2020-08
5. Charge controlled delay element enabled widely linear power efficient MPCG‐MDLL in 1.2V, 65nm CMOS;International Journal of Circuit Theory and Applications;2019-12-19
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