A 16B 5MS/s Pipeline-SAR ADC in 180nm CMOS-Reference-Cited by-同舟云学术

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A 16B 5MS/s Pipeline-SAR ADC in 180nm CMOS

Published:2023-12-15 Issue: Volume: Page:141-145
ISSN:
Container-title:2023 IEEE 6th International Conference on Electronics and Communication Engineering (ICECE)
language:
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Author:

Ma Siyuan¹,Su Qing¹,Li Runjie¹,Zhang Heng¹,Jia Hanbo²,Guo Xuan²,Wu Jin²

Affiliation:

1. University of Chinese Academy of Science,School of Integrated Circuits,Beijing,China,100049

2. Chinese Academy of Science,Institute of Microelectronics,Beijing,China,100029

Funder

Research and Development

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10462247/10462236/10462292.pdf?arnumber=10462292

Reference7 articles.

1. 3.7 A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier

2. A SAR-Assisted Two-Stage Pipeline ADC

3. A 0.05-mm² 110-μW 10-b self-calibrating successive approximation ADC core in 0.18-μm CMOS

4. High CMRR Voltage Mode Instrumentation Amplifier Using a New CMOS Differential Difference Current Conveyor Realization

5. CMOS Operational Floating Current Conveyor Circuit for Instrumentation Amplifier Application

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