Die to Wafer Hybrid Bonding for Chiplet and Heterogeneous Integration: Die Size Effects Evaluation-Small Die Applications

Author:

Gao Guilian1,Mirkarimi Laura1,Fountain Gill1,Suwito Dominik1,Theil Jeremy1,Workman Thomas1,Uzoh Cyprian1,Lee Bongsub1,Bang K.M.1,Guevara Gabe1

Affiliation:

1. Adeia,San Jose,USA

Publisher

IEEE

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Advancing Fine Pitch (< 5μm) Interconnects through Self-Aligned Die-to-Wafer Hybrid Bonding for Chiplet Integration;2023 IEEE 25th Electronics Packaging Technology Conference (EPTC);2023-12-05

2. Assembly process characterization of 3D Stacking of Heterogeneous Chiplets;2023 IEEE 25th Electronics Packaging Technology Conference (EPTC);2023-12-05

3. Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

4. Toward monolithic growth integration of nanowire electronics in 3D architecture: a review;Science China Information Sciences;2023-09-06

5. Surface Protecting and Particles Removing after Wafer Sawing for Die-to-wafer Hybrid Bonding;2023 24th International Conference on Electronic Packaging Technology (ICEPT);2023-08-08

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