Chiplet-based System PSI Optimization for 2.5D/3D Advanced Packaging Implementation
Author:
Affiliation:
1. Samsung Electronics Co. Ltd,FoundryBusinessDivision,Hwaseong-si,South Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816439.pdf?arnumber=9816439
Reference13 articles.
1. Foveros: 3D Integration and the use of Face-to-Face Chip Stacking for Logic Devices
2. SAINT-S - 3D SRAM Stacking Solution Based on TSV Technology;cho;2020IEEE Hotchip Symposium,0
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