Design and Analysis of 3D Heterogeneous Chiplet Stack for RF Front-End Module Minituarization-Reference-Cited by-同舟云学术

Design and Analysis of 3D Heterogeneous Chiplet Stack for RF Front-End Module Minituarization

Published:2023-05 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE 73rd Electronic Components and Technology Conference (ECTC)
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Author:

Rotaru Mihai Dragos¹,Tiwari Shashank²,Castillou Paul³,Chong Chai Tai¹,Jien Chui King¹

Affiliation:

1. Institute of Microelectronics (IME), Agency for Science, Technology, and Research (A*STAR),Singapore

2. GlobalFoundries,Bangalore,India

3. Qorvo,San Jose,United States

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10195193/10195244/10195439.pdf?arnumber=10195439

Reference6 articles.

1. 77GHz Cavity-Backed AiP Array in FOWLP Technology

2. System in package embedding III-V chips by fan-out wafer-level packaging for RF applications;guan;Proc IEEE Electronic Components and Technology Conf,0

3. Via-Last TSV (From Top) Fabrication on a LNA SOI Wafer for 3D Heterogenous Chiplet Integration;wang;Proc IEEE Electronics Packaging Technology Conf,0

4. Fabrication and RF Property Evaluation of High-Resistivity Si Interposer for 2.5-D/3-D Heterogeneous Integration of RF Devices

5. 3D FOWLP Integration;garnier;Proc IEEE Electronic Components and Technology Conf,0

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1. Vertical Stacking of Heterogeneous Chiplets of Duplexer on LNA/SOI;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. Process and Integration Challenges for Via Last TSV (from top) on Functional LNA SOI wafers for 3D Heterogeneous chiplet integration;2023 IEEE 25th Electronics Packaging Technology Conference (EPTC);2023-12-05