A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS-Reference-Cited by-同舟云学术

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A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS

Published:2018 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Nguyen Xuan-Thuan,Hoang Trong-Thuc,Nguyen Hong-Thu,Inoue Katsumi,Pham Cong-Kha

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8334884/8350884/08351406.pdf?arnumber=8351406

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Architectural analysis of 1-D to 2-D array conversion of priority encoder;International Journal of System Assurance Engineering and Management;2023-07-04

2. Architectural Improvement and Performance Evaluation of 1D-to-2D Array Conversion Priority Encoder;2022 International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2022-12-23

3. A Novel low power 2-D to 3-D Array Priority Encoder using Split-Logic Technique for Data Path Applications;WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL;2022-01-07

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