Study of Trap Models Related to the Variable Retention Time Phenomenon in DRAM-Reference-Cited by-同舟云学术

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Study of Trap Models Related to the Variable Retention Time Phenomenon in DRAM

Published:2011-06 Issue:6 Volume:58 Page:1643-1648
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Kim Heesang,Oh Byoungchan,Son Younghwan,Kim Kyungdo,Cha Seon-Yong,Jeong Jae-Goan,Hong Sung-Joo,Shin Hyungcheol

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/16/5770363/05759766.pdf?arnumber=5759766

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Divulge of Root Cause Failure in Individual Cells of 2× nm Technology DDR4 DRAM at Operating Temperature;IEEE Transactions on Electron Devices;2022-05

2. A Multiscale Statistical Evaluation of DRAM Variable Retention Time;2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2021-04-08

3. Reducing DRAM refresh power consumption by runtime profiling of retention time and dual-row activation;Microprocessors and Microsystems;2020-02

4. The study of relation between variable retention time and channel implantation;Microelectronic Engineering;2016-08

5. Extraction of Distance Between Interface Trap and Oxide Trap from Random Telegraph Noise in Gate-Induced Drain Leakage;Journal of Nanoscience and Nanotechnology;2016-05-01

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