Performance evaluation and design considerations of 2D semiconductor based FETs for sub-10 nm VLSI-Reference-Cited by-同舟云学术

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Performance evaluation and design considerations of 2D semiconductor based FETs for sub-10 nm VLSI

Published:2014-12 Issue: Volume: Page:
ISSN:
Container-title:2014 IEEE International Electron Devices Meeting
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Author:

Cao Wei,Kang Jiahao,Sarkar Deblina,Liu Wei,Banerjee Kaustav

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7038718/7046955/07047143.pdf?arnumber=7047143

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Realization of Extremely High-Gain and Low-Power in nMOS Inverter Based on Monolayer WS₂ Transistor Operating in Subthreshold Regime;ACS Nano;2024-08-15

2. Transport Properties and Device Performance of Quasi-One-Dimensional MoS2 FETs;2023 46th MIPRO ICT and Electronics Convention (MIPRO);2023-05-22

3. Tunneling Attenuation and Leakage Current in MoS₂ Nanoribbon MOSFETs;2023 46th MIPRO ICT and Electronics Convention (MIPRO);2023-05-22

4. Combined Influence of Gate Oxide and Back Oxide Materials on Self-Heating and DIBL Effect in 2D MOS2-Based MOSFETs;Applied Sciences;2023-05-17

5. Ultralow Subthreshold Swing 2D/2D Heterostructure Tunneling Field-Effect Transistor with Ion-Gel Gate Dielectrics;ACS Applied Electronic Materials;2022-12-29

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