Design of PLL using improved performance ring VCO-Reference-Cited by-同舟云学术

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Design of PLL using improved performance ring VCO

Published:2016-03 Issue: Volume: Page:
ISSN:
Container-title:2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)
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Author:

Suman Shruti,Sharma K. G.,Ghosh P. K.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7731602/7754737/07755351.pdf?arnumber=7755351

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Implementation of PLL with Dead Zone-Less Low-Power Phase Frequency Detector;International Journal of Innovative Science and Research Technology (IJISRT);2024-07-16

2. Design of a Novel PLL for Application in Distributed High Frequency Bands;2024 6th International Conference on Energy, Power and Environment (ICEPE);2024-06-20

3. Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology;Electronics;2023-02-03

4. Design of a fully integrated VHF CP‐PLL frequency synthesizer with an all‐digital defect‐oriented built‐in self‐test;The Journal of Engineering;2022-10-28

5. Design and Analysis of Two-stage CMOS LCD Buffer Operational Amplifier with Additional Load Capacitance;2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC);2022-08-17

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