Improved Dynamic Comparator With Adaptive Delay Line for the Latch Conduction and Regenerative Feedback Assisted FIA
Author:
Affiliation:
1. Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China,Chengdu,China
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10198027/10198028/10198166.pdf?arnumber=10198166
Reference7 articles.
1. A 174?VRMS Input Noise, 1 GS/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch;bindra;IEEE International Solid-State Circuits Conference ISSCC 2022,2022
2. A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s
3. A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time
4. An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier
5. A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise
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