A- 108dBm Sensitivity, -28dB SIR, 130nW to 41µW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver

Author:

Dissanayake Anjana,Moody Jesse,Bishop Henry L.,Truesdell Daniel,Muhlbauer Henry,Lu Ruochen,Gao Anming,Gong Songbin,Calhoun Benton H.,Bowers Steven M.

Publisher

IEEE

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Leveraging a Digital Chirp Spread Spectrum Detector for LPWAN Wake-Up Receivers;2024 14th International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP);2024-07-17

2. A 0.77mW 1.84nJ/bit Phase Noise Canceling Receiver for QAM and OFDM and Cellular IoT;2024 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2024-06-16

3. A Near-Zero Power Reconfigurable and Robust Multiband RF Wake-Up Receiver Achieving −108dBm Sensitivity Operating from −40° C to 70° C;2024 IEEE/MTT-S International Microwave Symposium - IMS 2024;2024-06-16

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