Tiling Imperfectly-nested Loop Nests

Author:

Ahmed N.,Mateev N.,Pingali K.

Publisher

IEEE

Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Cache Memory and On-Chip Cache Architecture: A Survey;Communications in Computer and Information Science;2024

2. An efficient tile size selection model based on machine learning;Journal of Parallel and Distributed Computing;2018-11

3. Efficient array slicing on the Intel Xeon Phi coprocessor;Proceedings of the 4th ACM SIGPLAN International Workshop on Libraries, Languages, and Compilers for Array Programming;2017-06-18

4. High-Performance Matrix-Matrix Multiplications of Very Small Matrices;Euro-Par 2016: Parallel Processing;2016

5. A Programming Language Interface to Describe Transformations and Code Generation;Languages and Compilers for Parallel Computing;2011

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