CTT-Based Scalable Neuromorphic Architecture
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, The Heterogeneous Integration Knowledge (THInK) Team, McGill University, Montreal, Canada
Funder
Natural Sciences and Engineering Research Council of Canada
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/5503868/10078357/10043852.pdf?arnumber=10043852
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2. Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications;IEEE Journal on Emerging and Selected Topics in Circuits and Systems;2023-12
3. Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12
4. Statistical Weight Refresh System for CTT-Based Synaptic Arrays;Proceedings of the Great Lakes Symposium on VLSI 2023;2023-06-05
5. Guest Editorial Unconventional Computing Techniques for Emerging Technology Applications;IEEE Journal on Emerging and Selected Topics in Circuits and Systems;2023-03
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