Unlocking Efficiency in BNNs: Global by Local Thresholding for Analog-Based HW Accelerators
Author:
Affiliation:
1. Design Automation for Embedded Systems Group, TU Dortmund University, Dortmund, Germany
2. DIMES Department, University of Calabria, Arcavacata, Italy
3. Chair of AI Processor Design, Technical University of Munich (TUM), Munich, Germany
Funder
Deutsche Forschungsgemeinschaft (DFG) through OneMemory Project
ACCROSS Project
Collaborative Research Center SFB 876 “Providing Information by Resource-Constrained Analysis”
Federal Ministry of Education and Research of Germany and the state of North Rhine-Westphalia as part of the Lamarr-Institute for ML and AI
PON Ricerca Innovazione-MUR through Ministero dell–Universitã e della Ricerca, Italian Government
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/5503868/10375869/10251514.pdf?arnumber=10251514
Reference28 articles.
1. Binarized neural networks;Hubara
2. Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks
3. Reliable Binarized Neural Networks on Unreliable Beyond Von-Neumann Architecture
4. Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization
5. Design and optimization of FeFET-based crossbars for binary convolution neural networks
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