Design of Power and Delay Efficient Fault Tolerant Adder-Reference-Cited by-同舟云学术

Design of Power and Delay Efficient Fault Tolerant Adder

Published:2023-02-02 Issue: Volume: Page:
ISSN:
Container-title:2023 Third International Conference on Artificial Intelligence and Smart Energy (ICAIS)
language:
Short-container-title:

Author:

C Kalamani¹,Perumal Vivek Karthick²,Vivek Kumar M.³,Muralidharan J.⁴

Affiliation:

1. Dr.Mahalingam College of Engineering and Technology,Department of ECE,Coimbatore,India

2. Sona College of Technology,Department of ECE,Salem,India

3. Sri Eshwar College of Engineering,Department of ECE,Coimbatore,India

4. KPR Institute of Engineering and Technology,Department of ECE,Coimbatore,India

Publisher

IEEE

Link

Reference12 articles.

2. Design and Implementation of Low Power Error Tolerant Adder;siddalingeshwar;International Journal of Electronic and Electrical Engineering,2014

3. VLSI Architeture For Barrel Distortion Correction In Surveillance Camera Images;mohankumar;Journal of Electronics and Computer Science,2015

5. VHDL based turbo encoder and decoder using cadence;kalamani;International Conference on Recent Trends in Engineering and Technology,2016

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High Speed Fault Tolerant Approximate Adder for Low Power Application;2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2024-05-17