Fast and processor efficient parallel matrix multiplication algorithms on a linear array with a reconfigurable pipelined bus system-Reference-Cited by-同舟云学术

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Fast and processor efficient parallel matrix multiplication algorithms on a linear array with a reconfigurable pipelined bus system

Published:1998 Issue:8 Volume:9 Page:705-720
ISSN:1045-9219
Container-title:IEEE Transactions on Parallel and Distributed Systems
language:
Short-container-title:IEEE Trans. Parallel Distrib. Syst.

Author:

Keqin Li ,Yi Pan ,Si Qing Zheng

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Signal Processing

Link

http://xplorestaging.ieee.org/ielx4/71/15311/00706044.pdf?arnumber=706044

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