Effects of bit line coupling on the faulty behavior of DRAMs

Author:

Al-Ars Z.,Hamdioui S.,van de Goor A.J.

Publisher

IEEE

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02

2. Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics;2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO);2020-10

3. HaRMony;Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems;2020-03-09

4. Content Aware Refresh: Exploiting the Asymmetry of DRAM Retention Errors to Reduce the Refresh Frequency of Less Vulnerable Data;IEEE Transactions on Computers;2019-03-01

5. Mitigating bitline crosstalk noise in DRAM memories;Proceedings of the International Symposium on Memory Systems;2017-10-02

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