A Study of AES Software Implementation for IoT Systems
Author:
Affiliation:
1. School of VLSI Design and Embedded System National Institute of Technology,Kurukshetra,India
2. National Institute of Technology,Electronics and Communication Engineering Department,Kurukshetra,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10064384/10064487/10064507.pdf?arnumber=10064507
Reference7 articles.
1. 340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS
2. Area-Efficient Nano-AES Implementation for Internet-of-Things Devices
3. Analysing the security-performance trade-offs in block ciphers;jindal;IEEE International conference on Computing Communication and Automation,0
4. An ultra-low power AES encryption core in 65 nm SOTB CMOS process;hoang;International SoC Design Conference,0
5. Low Power AES using 8-bit and 32-bit data path optimization for small Internet of things;sunwoo;Journal of Signal Processing Systems,2019
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