Pre-RTL Voltage and Power Optimization for Low-Cost, Thermally Challenged Multicore Chips
Author:
Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/8118206/8119172/08119277.pdf?arnumber=8119277
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Understanding Timing Error Characteristics from Overclocked Systolic Multiply–Accumulate Arrays in FPGAs;Journal of Low Power Electronics and Applications;2024-01-09
2. HW/SW Co-Optimization and Co-Protection;Synthesis Lectures on Digital Circuits & Systems;2024
3. An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration;2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN);2020-06
4. Exploiting Thermal Transients With Deterministic Turbo Clock Frequency;IEEE Computer Architecture Letters;2020-01-01
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