Author:
Hassani Arghavan Mohammad,Rezaalipour Morteza,Dehyadegari Masoud
Cited by
3 articles.
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1. A Timing-Aware Configurable Adder Based on Timing Detection for Low-Voltage Computing;IEEE Journal on Emerging and Selected Topics in Circuits and Systems;2023-03
2. Techniques for leakage power reduction using not and nand logic gates in tanner tool;1ST INTERNATIONAL CONFERENCE ON ADVANCES IN SIGNAL PROCESSING, VLSI, COMMUNICATIONS AND EMBEDDED SYSTEMS: ICSVCE-2021;2021
3. Exploiting Configurable Approximations for Tolerating Aging-induced Timing Violations;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2020-09-01