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Area-Optimized Constant-Time Hardware Implementation for Polynomial Multiplication

  • Published:2023-03 Issue:1 Volume:15 Page:5-8
  • ISSN:1943-0663
  • Container-title:IEEE Embedded Systems Letters
  • language:
  • Short-container-title:IEEE Embedded Syst. Lett.

Author:

Khan Safiullah1ORCID,Lee Wai-Kong2ORCID,Khalid Ayesha3,Majeed Abdul2,Hwang Seong Oun2ORCID

Affiliation:

1. Department of IT Convergence Engineering, Gachon University, Seongnam, South Korea

2. Department of Computer Engineering, Gachon University, Seongnam, South Korea

3. Centre for Secure Information Technologies (CSIT), Queen’s University Belfast, Belfast, U.K.

Funder

National Research Foundation of Korea Grant

Korea Government

EPSRC Quantum Communications Hub

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Computer Science,Control and Systems Engineering

Reference10 articles.

1. Efficient architecture and implementation for NTRUEncrypt system;liu;Proc IEEE 58th Int Midwest Symp Circuits Syst (MWSCAS),2015

2. Secure and Compact Full NTRU Hardware Implementation

3. A High-Speed Constant-Time Hardware Implementation of NTRUEncrypt SVES

4. An FPGA implementation of the NTRUEncrypt cryptosystem

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1. LAMP: Efficient Implementation of Lightweight Accelerator for Polynomial MultiPlication, From Falcon to RBLWE-ENC;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

2. FPGA Based Accelerator for Implementation of Large Integer Polynomials;International Journal of Innovative Science and Research Technology (IJISRT);2024-05-21

3. Data-Oblivious and Performant: On Designing Security-Conscious Hardware;2024 IEEE 25th Latin American Test Symposium (LATS);2024-04-09

4. Hardware Circuits and Systems Design for Post-Quantum Cryptography—A Tutorial Brief;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-03

5. Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories;IEEE Access;2024
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