An analytical back-gate bias effect model for ultrathin SOI CMOS devices
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx1/16/5233/00202788.pdf?arnumber=202788
Cited by 25 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. High-Voltage Analog Switch Inspired by Stacked MOSFET-Based RF Switches;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-11
2. Back Bias Induced Modeling of Subthreshold Characteristics of SOI Junctionless Field Effect Transistor (JLFET);Silicon;2020-07-14
3. Effect of Substrate Induced Surface Potential (SISP) on Threshold Voltage of SOI Junction-Less Field Effect Transistor (JLFET);Silicon;2019-05-28
4. Subthreshold Characteristic Analysis and Models for Tri-Gate SOI MOSFETs Using Substrate Bias Induced Effects;IEEE Transactions on Nanotechnology;2019
5. A Threshold Voltage Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects;IEEE Transactions on Electron Devices;2017-09
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