Modeling of Barrier-Engineered Charge-Trapping nand Flash Devices-Reference-Cited by-同舟云学术

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Modeling of Barrier-Engineered Charge-Trapping nand Flash Devices

Published:2010-06 Issue:2 Volume:10 Page:222-232
ISSN:1530-4388
Container-title:IEEE Transactions on Device and Materials Reliability
language:
Short-container-title:IEEE Trans. Device Mater. Relib.

Author:

Hang-Ting Lue ,Sheng-Chih Lai ,Tzu-Hsuan Hsu ,Pei-Ying Du ,Szu-Yu Wang ,Kuang-Yeu Hsieh ,Liu Rich,Chih-Yuan Lu

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/7298/5477199/05406149.pdf?arnumber=5406149

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Strategies for a Wide Memory Window of Ferroelectric FET for Multilevel Ferroelectric VNAND Operation;IEEE Electron Device Letters;2024-07

2. Channel Potential of Bandgap-Engineered Tunneling Oxide (BE-TOX) in Inhibited 3D NAND Flash Memory Strings;Electronics;2024-04-20

3. A Compact Model for Program Operation of Gate-All-Around Barrier-Engineered Charge-Trapping NAND Flash Memories;2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2024-03-03

4. Investigation of endurance degradation for 3-D charge trap NAND flash memory with bandgap-engineered tunneling oxide;IEICE Electronics Express;2022-12-25

5. Fabrication of a Hole‐Type Vertical Resistive‐Switching Random‐Access Array and Intercell Interference Induced by Lateral Charge Spreading;Advanced Electronic Materials;2022-12-23

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