Design and Implementation of Low-Power and Area-Efficient Flip Flop with Redundant Pre-Charge Free Operation-Reference-Cited by-同舟云学术

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Design and Implementation of Low-Power and Area-Efficient Flip Flop with Redundant Pre-Charge Free Operation

Published:2023-09-20 Issue: Volume: Page:
ISSN:
Container-title:2023 4th International Conference on Smart Electronics and Communication (ICOSEC)
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Author:

Vishal R.¹,Vidyanidhi P. Sri¹,Deepak R.¹,Agrawal Sonali¹

Affiliation:

1. Amrita School of Engineering, Bengaluru, Amrita Vishwa Vidyapeetham,Department of Electronics and Communication Engineering,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10275782/10275807/10276081.pdf?arnumber=10276081

Reference15 articles.

1. Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure

2. A faster phase frequency detector using transmission gate-based latch for the reduced response time of the PLL

3. 4-bit Counter Using High-Speed Low-Voltage CML D-Flipflops

4. Low-power High-speed Folded MCML-based Frequency Divider for High-frequency Applications

5. Design, Implementation and Performance Comparison of D-Latch Using Different Topologies;gupta;6th International Conference on Communication and Electronics Systems (ICCES),2021

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Power Efficiency Evaluation of Dual Edge Triggered Flip-Flops - A Comparative Analysis;2024 7th International Conference on Devices, Circuits and Systems (ICDCS);2024-04-23

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