Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning-Reference-Cited by-同舟云学术

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Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning

Published:2021-11 Issue: Volume: Page:
ISSN:
Container-title:2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
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Author:

Cheng Chung-Kuan,Ho Chia-Tung,Holtz Chester,Lin Bill

Funder

NSF

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9667779/9667550/09667812.pdf?arnumber=9667812

Reference23 articles.

1. Sp&r: Smt-based simultaneous place-route for standard cell synthesis of advanced nodes;lee;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2020

2. The interpretation and application of Rent's rule

3. A routability-driven complimentary-FET (CFET) standard cell synthesis framework using SMT

4. Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Enhancement of ISPP Efficiency Using Neural Network-Based Optimization of 3-D NAND Cell;IEEE Transactions on Electron Devices;2023-07

3. Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-08

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