Quantified tabbed lines and ground void impact on real DDR5 eye margin
Author:
Affiliation:
1. Intel Microelectronics Asia LLC., Taiwan 20F., No.369, Sec. 7, Zhongxiao E. Rd., Nangang Dist.,Data Center Platform Application Engineer,Taipei City,Taiwan (R.O.C.),115
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9966654/9966628/09966713.pdf?arnumber=9966713
Reference5 articles.
1. MRC training vs. board defect
2. Far-End Crosstalk Mitigation in DDR5 Using Graphene-Paraffin Material Coated Signal Lines with Tabs
3. Quantified system level threshold methodology
4. Far-End Crosstalk Mitigation Using Homogeneous Dielectric Substrate in DDR5
5. Crosstalk mitigation and impedance management using tabbed lines;kunze;Intel,2015
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