An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor-Reference-Cited by-同舟云学术

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An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor

Published:2019-12 Issue: Volume: Page:
ISSN:
Container-title:2019 International Conference on Field-Programmable Technology (ICFPT)
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Author:

Mashimo Susumu,Inoue Koji,Shioya Ryota,Fujita Akifumi,Matsuo Reoma,Akaki Seiya,Fukuda Akifumi,Koizumi Toru,Kadomoto Junichiro,Irie Hidetsugu,Goshima Masahiro

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8961924/8977829/08977924.pdf?arnumber=8977924

Cited by 25 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Towards Trustworthy RISC-V Designs: Formal Verification of the MFENCE Instruction;2024 4th Interdisciplinary Conference on Electrics and Computer (INTCEC);2024-06-11

2. Ensuring SFENCE Instruction Correctness: A Formal Verification Framework Based on Invariants;2024 IEEE International Conference on Electro Information Technology (eIT);2024-05-30

3. A 0.11pJ/bit read energy embedded NanoBridge non-volatile memory and its integration in a 28 nm 32 bit RISC-V microcontroller units;Japanese Journal of Applied Physics;2024-01-19

4. W-IQ: Wither-logic based issue queue for RISC-V superscalar out-of-order processor;Integration;2024-01

5. SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

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