Design of Quaternary Inverter Using 32nm SOI Technology

Author:

Sagar Diksha1,Sannamani Shweta C1,A Chand Pasha1,Patel K S Vasundhara1,N Manjunath M1

Affiliation:

1. BMS College of Engineering,Department of Electronics and Communication,Bengaluru,India

Publisher

IEEE

Reference22 articles.

1. Design of novel Multiple Valued Logic (MVL) circuits

2. SOI-based devices and technologies for High Voltage ICs

3. Introduction to Semiconductor Devices for Computing and Telecommunications Applications;brennan,2005

4. MVL ALU based on QSD Technique;deshmukh,2015

5. Performance analysis of FinFET and negative capacitance FET over 6T SRAM

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and analysis of a novel compact quaternary adder;International Journal of System Assurance Engineering and Management;2024-04-12

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