A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW

Author:

Kauffman John G.,Witte Pascal,Lehmann Matthias,Becker Joachim,Manoli Yiannos,Ortmanns Maurits

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 38 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Using Negative-R Assisted Integrators in Wide-band Delta-Sigma Modulators;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Bitwise ELD Compensation in Δ∑ Modulators;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

3. Complexity Reduced LUT-Based DAC Correction in Continuous-Time Delta-Sigma Modulators;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

4. Wideband and Low-Power Delta-Sigma ADCs: State of the Art, Trends and Implementation Examples;ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC);2021-09-13

5. Efficient Offline Outer/Inner DAC Mismatch Calibration in Wideband ΔΣ ADCs;IEEE Transactions on Circuits and Systems I: Regular Papers;2020-12

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