C-JFET OpAmp on “Folded” Cascode with Compensation Channel for the Systematic Component of the Zero Bias Voltage
Author:
Affiliation:
1. Don State Technical University,Rostov-on-Don,Russia
2. Don State Technical University,IPPM RAS,Rostov-on-Don,Zelenograd,Russia
Funder
Russian Science Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9802078/9801892/09802383.pdf?arnumber=9802383
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1. Temperature drift stabilized filter circuit;ariyoshi,1997
2. Zero Drift Infrared Radiation Thermometer Using Chopper Stabilised Pre-Amplifier
3. Complementary logic with 60 nm poly gate JFET for 0.5 V operation
4. Complementary JFET Logic for Low-Power Applications in Extreme Environments
5. SiC Vertical-Channel n- and p-JFETs Fully Fabricated by Ion Implantation
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. The Circuit Technique for Reducing the Zero Level of the JFET Op-Amp on the Push-Pull Folded-Cascode;2022 IEEE International Multi-Conference on Engineering, Computer and Information Sciences (SIBIRCON);2022-11-11
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