Low-power high-performance double-gate fully depleted SOI circuit design
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx5/16/21545/00998595.pdf?arnumber=998595
Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Si 3 N 4 :HfO 2 dual‐k spacer bulk planar junctionless transistor for mixed signal integrated circuits;IET Circuits, Devices & Systems;2018-08-30
2. Design Device for Subthreshold Slope in DG Fully Depleted SOI MOSFET;Journal of Nano- and Electronic Physics;2017
3. DSOI—a novel structure enabling adjust circuit dynamically;Journal of Semiconductors;2016-06
4. Bias dependence of TID induced single transistor latch for 0.13 μm partially depleted SOI input/output NMOSFETs;Microelectronics Reliability;2016-01
5. New analytical models of subthreshold surface potential and subthreshold current of fully depleted short-channel silicon-on-insulator MOSFETs with halo or pocket implantation;Japanese Journal of Applied Physics;2014-05-01
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