Single-Event Transient (SET) sensitivity into the Clock Networks of FPGAs-Reference-Cited by-同舟云学术

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Single-Event Transient (SET) sensitivity into the Clock Networks of FPGAs

Published:2021-09 Issue: Volume: Page:
ISSN:
Container-title:2021 21th European Conference on Radiation and Its Effects on Components and Systems (RADECS)
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Author:

Guibbaud N.¹,Miller F.¹,Colladant T.²

Affiliation:

1. Nuclétudes,France

2. DGA,Paris,France

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9954459/9954461/09954548.pdf?arnumber=9954548

Reference10 articles.

1. FPGA Basics and FPGA SEE Testing;rezzak;Microsemi,0

2. SmartFusion2 and IGLOO2 Neutron Single Event Effects(SEE),2020

3. SmartFusion2 and IGLOO2 Cloking Resources;Revision 0 8,0

4. PolarFire FPGA Clocking Resources;Revision 5 0 Microsemi,0

5. Soft-Error Probability Due toSET in Clock Tree Networks;chipana;IEEE Computer Society Annual Symposium on VLSI,2012

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1. A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays;Sensors;2024-08-19

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