A 1.41-pJ/b 56-Gb/s PAM-4 Receiver Using Enhanced Transition Utilization CDR and Genetic Adaptation Algorithms in 7-nm CMOS-Reference-Cited by-同舟云学术

A 1.41-pJ/b 56-Gb/s PAM-4 Receiver Using Enhanced Transition Utilization CDR and Genetic Adaptation Algorithms in 7-nm CMOS

Published:2019-11 Issue:11 Volume:2 Page:248-251
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Dehlaghi Behzad^ORCID,Tang Kerry,Chan Carusone Anthony,Cassan David,Tonietto Davide,Shahramian Shayan,Liang Joshua,Bespalko Ryan,Dunwell Dustin,Bailey James,Wang Bo,Sharif-Bakhtiar Alireza,O'Farrell Michael

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8011414/8911531/08821332.pdf?arnumber=8821332

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4. PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-05

5. A Novel High-Gain PAM4 Baud-Rate Phase Detector for ADC-Based CDR;2022 7th International Conference on Integrated Circuits and Microsystems (ICICM);2022-10-28