LDO Regulator Optimized on Power Efficiency and Load Transient Response with Voltage Damper and Body Loop Feedback-Reference-Cited by-同舟云学术

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LDO Regulator Optimized on Power Efficiency and Load Transient Response with Voltage Damper and Body Loop Feedback

Published:2022-05-28 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Kim Heebae,Kwak Seung Soo,Kim Yong Sin

Funder

National Research Foundation

Ministry of Education

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937778.pdf?arnumber=9937778

Reference8 articles.

1. A Power Efficient Output Capacitor-Less LDO Regulator with Auto-Low Power Mode and Using Feed-Forward Compensation

2. A 1.66 mV FOM Output Cap-Less LDO With Current-Reused Dynamic Biasing and 20 ns Settling Time

3. A Digital LDO Regulator With a Self-Clocking Burst Logic for Ultralow Power Applications

4. A High Power Supply Rejection and Fast Settling Time Capacitor-Less LDO

5. Design of Analog CMOS Integrated Circuits;razavi,2001

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Capacitor-Less Low-Dropout Regulator with PVT Compensated Adaptive Biasing;2024 IEEE 14th Symposium on Computer Applications & Industrial Electronics (ISCAIE);2024-05-24

2. A Transient Enhanced Output Capacitor-Less LDO With Adaptive Biasing and Spike Reduction;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17

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