Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation-Reference-Cited by-同舟云学术

Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation

Published:2023-04 Issue:4 Volume:70 Page:1439-1449
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Aiello Orazio¹^ORCID,Crovetti Paolo Stefano²^ORCID,Alioto Massimo³^ORCID

Affiliation:

1. Electrical, Electronics and Telecommunication Engineering and Naval Architecture Department (DITEN), University of Genoa, Genoa, Italy

2. Department of Electronics and Telecommunications (DET), Politecnico di Torino, Turin, Italy

3. Department of Electrical and Computer Engineering, National University of Singapore, Queenstown, Singapore

Funder

Singapore Ministry of Education

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10089883/10026247.pdf?arnumber=10026247

Reference37 articles.

1. An Energy-Efficient Hybrid SAR-VCO $\Delta \Sigma $ Capacitance-to-Digital Converter in 40-nm CMOS

2. A Micropower $\Delta\Sigma$-Based Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer

3. An 8.2-$\mu$ W 0.14-mm2 16-Channel CDMA-Like Capacitance-to-Digital Converter

4. A 0.026mm2 capacitance-to-digital converter for biotelemetry applications using a charge redistribution technique;tanaka;Proc IEEE Asian Solid-State Circuits Conf,2007

5. An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter

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