Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS-Reference-Cited by-同舟云学术

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Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS

Published:1999 Issue:8 Volume:34 Page:1074-1083
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Djahanshahi H.,Hansen F.,Salama C.A.T.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/16876/00777105.pdf?arnumber=777105

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High-speed driver with built-in self detection functions for off-chip transmission;Analog Integrated Circuits and Signal Processing;2012-06-14

2. Design and realization of 1.3 Gb/s off-chip transmission circuitry using 0.35 μm CMOS technology;Analog Integrated Circuits and Signal Processing;2011-07-17

3. Voltage-Mode 1.5 Gbps Interface Circuits for Chip-to-Chip Communication;ETRI Journal;2005-02-11

4. 1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-μm CMOS;IEEE Journal of Solid-State Circuits;2001-06

5. A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission;IEEE Journal of Solid-State Circuits;2000-06

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