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Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis

  • Published:2020-11 Issue:11 Volume:39 Page:3736-3747
  • ISSN:0278-0070
  • Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • language:
  • Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Ferretti LorenzoORCID,Kwon Jihye,Ansaloni Giovanni,Guglielmo Giuseppe Di,Carloni Luca P.,Pozzi Laura

Funder

National Science Foundation

MagicISEs

ML-Edge projects evaluated by the Swiss NSF

MyPreHealth

Hasler Stiftung

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Review of neural network model acceleration techniques based on FPGA platforms;Neurocomputing;2024-12

2. SEER: Super-Optimization Explorer for High-Level Synthesis using E-graph Rewriting;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2;2024-04-27

3. Investigating the Effect of Hyper-Parameter Settings on Simulated Annealing-Based High-Level Synthesis Design Space Exploration;2024 IEEE 17th Dallas Circuits and Systems Conference (DCAS);2024-04-19

4. A Testing Program and Pragma Combination Selection Based Framework for High-Level Synthesis Tool Pragma-Related Bug Detection;IEEE Transactions on Software Engineering;2024-04

5. Fast and Inexpensive High-Level Synthesis Design Space Exploration: Machine Learning to the Rescue;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11
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