Proposed Standardization of Heterogenous Integrated Chiplet Models

Author:

Mastroianni Anthony1,Kerr Benjamin2,Nasrullah Jawad3,Cameron Kevin4,Wong Hockshan James5,Ratchkov David6,Reynick Joseph7ORCID

Affiliation:

1. Siemens EDA, Siemens DISW,Advanced Packaging Solutions Director,NJ,USA

2. Google Cloud, Google LLC,Mountain View,CA,USA

3. Palo Alto Electron, Inc.,Palo Alto,CA,USA

4. Cameron EDA,R&D,Sunnyvale,CA,USA

5. Palo Alto Electron,Engineering Department,Palo Alto,CA,USA

6. Thrace Systems,San Jose,CA,USA

7. Tessent Silicon Lifecycle Solutions, Siemens DISW,State College,PA,USA

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

2. On Hardware Security and Trust for Chiplet-Based 2.5D and 3D ICs: Challenges and Innovations;IEEE Access;2024

3. A Novel Method for Mapping Parallel Vector-Scalar Multiplication on CGRA;2023 IEEE 6th International Conference on Electronics and Communication Engineering (ICECE);2023-12-15

4. A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication;International Journal of Circuit Theory and Applications;2023-09-06

5. Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products;2022 IEEE International Test Conference (ITC);2022-09

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