A simulation study about the memory operation of 3D-stacked capacitor-less 1T DRAM cells based on ferroelectric field-effect transistors (FeFETs)
Author:
Affiliation:
1. Sogang University,Department of Electronic Engineering,Seoul,Republic of Korea
Funder
National Research Foundation
IC Design Education Center
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10395912/10395932/10396222.pdf?arnumber=10396222
Reference10 articles.
1. Science and research policy at the end of Moore’s law
2. Advanced Capacitor Dielectrics: Towards 2x nm DRAM
3. The Smallest Engine Transforming Humanity: The Past, Present, and Future
4. A 3D Stackable DRAM: Capacitor-less Three-Wordline Gate-Controlled Thyristor (GCT) RAM with >40 μ A Current Sensing Window, >1010 Endurance, and 3-second Retention at Room Temperature
5. Design of a Capacitorless DRAM Based on Storage Layer Separated Using Separation Oxide and Polycrystalline Silicon
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