Gate Resistance Test Structures Bounded by Local Layout Density to Characterize Metal Gate Height Variation in 7nm FinFET Technology-Reference-Cited by-同舟云学术

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Gate Resistance Test Structures Bounded by Local Layout Density to Characterize Metal Gate Height Variation in 7nm FinFET Technology

Published:2024-05-13 Issue: Volume: Page:1-4
ISSN:
Container-title:2024 IEEE 33rd Microelectronics Design & Test Symposium (MDTS)
language:
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Author:

Zhu Hai¹,Onishi Katsunori¹,Tzou Thomas¹,Fayaz Mohammed Fazil¹,Jeong Byoung-Wook²,Lim Seong-Joon²,Chidambarrao Dureseti³

Affiliation:

1. IBM Infrastructure, IBM Corp,Poughkeepsie,NY,USA

2. Samsung Electronics Co. Ltd.,Hwasung-City,Gyeonggi-Do,Republic of Korea

3. IBM Research, IBM Corp,Yorktown Heights,NY,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10570095/10570103/10570132.pdf?arnumber=10570132

Reference3 articles.

1. Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications

2. Enhanced Reliability of 7-nm Process Technology Featuring EUV

3. Design and Analysis of Discrete FET Monitors in 7nm FinFET Product for Robust Technology Validation

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