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Understanding yield losses in logic circuits

Published:2004-05 Issue:3 Volume:21 Page:208-215
ISSN:0740-7475
Container-title:IEEE Design and Test of Computers
language:en
Short-container-title:IEEE Des. Test. Comput.

Author:

Appello D.,Fudoli A.,Giarda K.,Tancorre V.,Gizdarski E.,Mathew B.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software,Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/54/28929/01302087.pdf?arnumber=1302087

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Diagnosis of Scan Logic and Diagnosis Driven Failure Analysis[1];Microelectronics Failure Analysis;2019

2. Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs;2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC);2017-05

3. Identifying design systematics using learning based diagnostic analysis;2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC);2010-07

4. Doubling Test Cell Throughput by On-Loadboard Hardware- Implementation and Experience in a Production Environment;2009 14th IEEE European Test Symposium;2009-05

5. The Grand Pareto: A Methodology for Identifying and Quantifying Yield Detractors in Volume Semiconductor Manufacturing;IEEE Transactions on Semiconductor Manufacturing;2007-05

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