Performance Improvement of 16 Bus System using Hybrid Power Flow Controller
Author:
Affiliation:
1. St. Joseph’s Institute of Technology,Chennai
2. SIMATS,Saveetha School of Engineering,Chennai
3. Sethu Institute of Technology,Kariapatti
4. Research Scholar,Chennai
5. Sri Sairam Institute Of Technology,Chennai
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10028980/10028739/10029013.pdf?arnumber=10029013
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4. Analysis of Low Complexity Memory Footprint Reduction for Delay and Area Efficient Realization of 2D FIR Filters;sudhashree;International Journal of Applied Engineering Research,2015
5. Thyristor-Based FACTS Controllers for Electrical Transmission Systems
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