An empirical evaluation of High-Level Synthesis languages and tools for database acceleration

Author:

Arcas-Abella Oriol,Ndu Geoffrey,Sonmez Nehir,Ghasempour Mohsen,Armejach Adria,Navaridas Javier,Wei Song ,Mawer John,Cristal Adrian,Lujan Mikel

Publisher

IEEE

Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Neural Network Compiler for Parallel High-Throughput Simulation of Digital Circuits;2023 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2023-05

2. Automatic Transpiler that Efficiently Converts Digital Circuits to a Neural Network Representation;2022 International Joint Conference on Neural Networks (IJCNN);2022-07-18

3. Beyond Verilog: Evaluating Chisel versus High-level Synthesis with Tiny Designs;2022 23rd International Symposium on Quality Electronic Design (ISQED);2022-04-06

4. Implementing Synthetic Aperture Radar Backprojection in Chisel – A Field Report;Lecture Notes in Computer Science;2022

5. A Hardware Co-design Workflow for Scientific Instruments at the Edge;Driving Scientific and Engineering Discoveries Through the Integration of Experiment, Big Data, and Modeling and Simulation;2022

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